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HUFA75433S3S
March 2002
HUFA75433S3S
N-Channel UltraFET(R) MOSFETs 60V, 64A, 16m
General Description
These N-Channel power MOSFETs are manufactured using the innovative UltraFET(R) process. This advanced process technology achieves very low on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching convertors, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and battery-operated products.
Applications
* Motor and Load Control * Powertrain Management
Features
* 175C Maximum Junction Temperature * UIS Capability (Single Pulse and Repetitive Pulse) * Ultra-Low On-Resistance rDS(ON) = 0.016, VGS = 10V
D
D
G S TO-263AB
FDB Series
G S
MOSFET Maximum Ratings TC = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TC = 25oC, VGS = 10V) Continuous (TC = 125oC, VGS = 10V, RJA = 43oC/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 64 5 Figure 4 250 150 1 -55 to 175 A A A mJ W W/oC
oC
Ratings 60 20
Units V V
Thermal Characteristics
RJC RJA RJA Thermal Resistance Junction to Case TO-263 Thermal Resistance Junction to Ambient TO-263 Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 1 62 43
o o
C/W C/W
oC/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75433S3S
Package Marking and Ordering Information
Device Marking 75433S3 75433S3 Device HUFA75433S3ST HUFA75433S3S Package TO-263 TO-263 Reel Size 330mm Tube Tape Width 24mm N/A Quantity 800 units 50 units
Electrical Characteristics TC = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 55V, VGS = 0V VDS = 45V VGS = 0V VGS = 20V TC= 150oC 60 1 250 100 A nA V
On Characteristics
VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 64A, VGS = 10V ID = 64A, VGS = 10V, TJ = 175oC 2 0.013 0.029 4 0.016 0.035 V
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(10) Qg(TH) Qgs Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 20V Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge (VGS = 10V) VDD = 30V, ID = 64A VGS = 10V, RGS = 6.2 11 92 39 26 155 98 ns ns ns ns ns ns VDS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 20V VGS = 0V to 10V V = 30V DD VGS = 0V to 2V ID = 64A Ig = 1.0mA 1550 540 150 90 50 3 6 20 117 65 3.9 pF pF pF nC nC nC nC nC
Switching Characteristics
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 64A ISD = 32A ISD = 64A, dISD/dt = 100A/s ISD = 64A, dISD/dt = 100A/s 1.25 1.0 37 42 V V ns nC
Notes: 1: Starting TJ = 25C, L = 200H, IAS = 50A
(c)2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75433S3S
Typical Characteristics TC = 25C unless otherwise noted
1.2 POWER DISSIPATION MULTIPLIER 70 60 ID, DRAIN CURRENT (A) 0 25 50 75 100 125 150 175 50 40 30 20 10 0 TC , CASE TEMPERATURE (oC) 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC)
1.0
0.8
0.6
0.4
0.2
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 ZJC, NORMALIZED THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 10-1 100 101
SINGLE PULSE 0.01 10-5 10-4 t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
800 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION IDM, PEAK CURRENT (A)
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150
VGS = 20V
100
VGS = 10V
50 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
Figure 4. Peak Current Capability
(c)2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75433S3S
Typical Characteristics TC = 25C unless otherwise noted
1000 1000 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 STARTING TJ = 25oC
100s 100
1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TC = 25oC 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
STARTING TJ = 150oC 10
10ms
1 0.001 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Fairchild Application Notes AN7514 and AN7515.
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching Capability
100
100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID , DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 75
VGS = 20V
VGS = 10V VGS = 6V
75
50 TJ = 175oC 25 TJ = 25oC TJ = -55oC 0 3.0 3.5 4.0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V) 6.0
50 VGS = 5V
25
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC
0 0 0.5 1.0 1.5 2.0 VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE 2.0 1.2
Figure 8. Saturation Characteristics
VGS = VDS, ID = 250A
1.0
1.5
0.8
1.0
VGS = 10V, ID = 64A 0.5 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) 0.6 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs Junction Temperature
(c)2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75433S3S
Typical Characteristics TC = 25C unless otherwise noted
1.2 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 4000 CISS = CGS + CGD C, CAPACITANCE (pF)
1.1
1000
CRSS = CGD
COSS CDS + CGD
1.0
100 VGS = 0V, f = 1MHz 0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) 60 0.1 1 10 60 VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 30V 8
Figure 12. Capacitance vs Drain to Source Voltage
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 64A ID = 40A 0 10 20 30 40 50
2
0 Qg, GATE CHARGE (nC)
Figure 13. Gate Charge Waveforms for Constant Gate Currents
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG IAS VDD VDD tP VDS
+
IAS 0.01 0 tAV
Figure 14. Unclamped Energy Test Circuit
Figure 15. Unclamped Energy Waveforms
(c)2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75433S3S
Test Circuits and Waveforms (Continued)
VDS RL
VDD VDS
Qg(TOT)
VGS = 20V VGS
+
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS =10V
DUT Ig(REF)
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH
90% 50%
Figure 18. Switching Time Test Circuit
Figure 19. Switching Time Waveforms
(c)2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75433S3S
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T JM - T A ) P DM = ----------------------------RJA
80 RJA = 26.51+ 19.84/(0.262+Area)
60 RJA (oC/W) 40 20 0.1 1 AREA, TOP COPPER AREA (in2) 10
(EQ. 1)
In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.
Figure 20. Thermal Resistance vs Mounting Pad Area
R JA = 26.51 + ------------------------------------
19.84 ( 0.268 + Area )
(EQ. 2)
(c)2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75433S3S
PSPICE Electrical Model
.SUBCKT HUFA75433S3S CA 12 8 2.5e-9 CB 15 14 2.8e-9 CIN 6 8 1.4e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 65.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
LGATE
February 2002
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + 6 8 13 8 S2A 14 13 S2B CB + EDS 5 8 8 22 RVTHRES 14 IT VBAT + 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 21 16 MWEAK MMED EBREAK RLDRAIN DBREAK 11 + 17 18 DBODY 5 DRAIN 2
RSLC2
5 51 ESG + GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 6 8 -
IT 8 17 1 LGATE 1 9 6.57e-9 LDRAIN 2 5 1e-9 LSOURCE 3 7 3.4e-9 RLGATE 1 9 65.7 RLDRAIN 2 5 10 RLSOURCE 3 7 34
MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.7e-3 RGATE 9 20 1.53 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 6.9e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1
EGS
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*215),2.5))} .MODEL DBODYMOD D (IS = 1.3e-12 RS = 3.05e-3 TRS1 = 2.4e-3 TRS2 = 1.5e-7 CJO = 1.92e-9 TT = 5e-9 M = 0.50 XTI=4.5) .MODEL DBREAKMOD D (RS = 2.2 TRS1 = 2.4e-3 TRS2 = -2e-5) .MODEL DPLCAPMOD D (CJO = 1.93e-9 IS = 1e-30 N = 10 M = 0.79) .MODEL MmedMOD NMOS (VTO=2.93 KP=2.6 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.53) .MODEL MstroMOD NMOS (VTO=3.55 KP=70 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.62 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15.3 RS=0.1) .MODEL RBREAKMOD RES (TC1 =1.2e-3 TC2 = -1.7e-8) .MODEL RDRAINMOD RES (TC1 = 2e-2 TC2 = 5.1e-5) .MODEL RSLCMOD RES (TC1 = 3e-3 TC2 = 2.9e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTEMPMOD RES (TC1 = -2.8e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.1e-3 TC2 = -1.1e-5) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6 VOFF= -3) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -6) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.4 VOFF= 0.3) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.3 VOFF= -0.4) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2002 Fairchild Semiconductor Corporation
+
Rev. A
HUFA75433S3S
SABER Electrical Model
REV February 2002 template HUFA75433S3S n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.3e-12,rs=3.05e-3,trs1=2.4e-3,trs2=1.5e-7,cjo=1.92e-9,tt=5e-9,m=0.50,xti=4.5) dp..model dbreakmod = (rs=2.2,trs1=2.4e-3,trs2=-2e-5) dp..model dplcapmod = (cjo=1.93e-9,isl=10e-30,nl=10,m=0.79) m..model mmedmod = (type=_n,vto=2.93,kp=2.6,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=3.55,kp=70,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.62,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6,voff=-3) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-6) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.3) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.4) c.ca n12 n8 = 2.5e-9 c.cb n15 n14 = 2.8e-9 DPLCAP 5 c.cin n6 n8 = 1.4e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 65.5 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 6.57e-9 l.ldrain n2 n5 = 1e-9 l.lsource n3 n7 = 3.4e-9 res.rlgate n1 n9 = 65.7 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 34
CA m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u S1A 12 13 8 S1B 13 + EGS 6 8 S2A 14 13 S2B CB + EDS 5 8 8 RVTHRES 14 IT VBAT + 22 10 RSLC1 51 RSLC2 ISCL ESG + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 6 6 8 50 RDRAIN EVTHRES 16 21 + 19 8 MMED MSTRO 8 DBREAK 11 DBODY MWEAK EBREAK + 17 18 RLDRAIN
LDRAIN DRAIN 2
LSOURCE 7 RLSOURCE 18 RVTEMP 19
SOURCE 3
RSOURCE RBREAK 17
15
res.rbreak n17 n18 = 1, tc1=1.2e-3,tc2=-1.7e-8 res.rdrain n50 n16 = 2.7e-3, tc1=2e-2,tc2=5.1e-5 res.rgate n9 n20 = 1.53 res.rslc1 n5 n51 = 1e-6, tc1=3e-3,tc2=2.9e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 6.9e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-2.1e-3,tc2=-1.1e-5 res.rvtemp n18 n19 = 1, tc1=-2.8e-3,tc2=1e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/215))** 2.5))} }
(c)2002 Fairchild Semiconductor Corporation
Rev. A
HUFA75433S3S
SPICE Thermal Model
REV 23 February 2002 HUFA75433S3 CTHERM1 TH 6 4.9e-4 CTHERM2 6 5 4.5e-3 CTHERM3 5 4 6.0e-3 CTHERM4 4 3 8.5e-3 CTHERM5 3 2 0.8e-2 CTHERM6 2 TL 4.2e-2 RTHERM1 TH 6 6.0e-4 RTHERM2 6 5 6.8e-3 RTHERM3 5 4 3.3e-2 RTHERM4 4 3 9.9e-2 RTHERM5 3 2 3.3e-1 RTHERM6 2 TL 3.5e-1
th
JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model HUFA75433S3 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =4.9e-4 ctherm.ctherm2 6 5 =4.5e-3 ctherm.ctherm3 5 4 =6.0e-3 ctherm.ctherm4 4 3 =8.5e-3 ctherm.ctherm5 3 2 =0.8e-2 ctherm.ctherm6 2 tl =4.2e-2 rtherm.rtherm1 th 6 =6.0e-4 rtherm.rtherm2 6 5 =6.8e-3 rtherm.rtherm3 5 4 =3.3e-2 rtherm.rtherm4 4 3 =9.9e-2 rtherm.rtherm5 3 2 =3.3e-1 rtherm.rtherm6 2 tl =3.5e-1 }
RTHERM3 CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2002 Fairchild Semiconductor Corporation
Rev. A
TRADEMARKS
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
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Rev. H5

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